| Lecture |
Topic |
PDF |
| Lecture 1 |
Introduction |
LECT01.pdf |
| Lecture 2 |
Introduction
to Logic Circuits: Variables, functions, truth tables, gates and networks |
LECT02.pdf |
| Lecture 3 |
Introduction
to Logic Circuits: Boolean algebra |
LECT03.pdf |
| Lecture 4 |
Introduction
to Logic Circuits: Synthesis using AND, OR, and NOT gates |
LECT04.pdf |
| Lecture 5 |
Introduction
to Logic Circuits: Design Examples |
LECT05.pdf |
| Lecture 6 |
Introduction
to Logic Circuits: CAD Tools and VHDL |
LECT06.pdf |
| Lecture 7 |
Optimized
Implementation of Logic Functions: Karnaugh Maps and Minimum Sum-of-Product
Forms |
LECT07.pdf |
| Lecture 8 |
Optimized
Implementation of Logic Functions: Strategy for Minimization, Minimum
Product-of-Sums Forms, Incompletely Specified Functions |
LECT08.pdf |
| Lecture 9 |
Optimized
Implementation of Logic Functions: Multiple Output Circuits, NAND and NOR
Logic Networks |
LECT09.pdf |
| Lecture 10 |
Implementation
Technology: Standard Chips and Programmable Logic Devices |
LECT10.pdf |
| Lecture 11 |
Implementation
Technology: Look-up Tables, XOR and XNOR gates |
LECT11.pdf |
| Lecture 12 |
Implementation
Technology: Buffers, Tri-state gates, Transmission gates |
LECT12.pdf |
| Lecture 13 |
Implementation
Technology: NMOS and PMOS Transistors, CMOS logic gates |
LECT13.pdf |
| Lecture 14 |
Optimized
Implementation of Logic Functions: Multilevel Synthesis and Analysis |
LECT14.pdf |
| |
Exam
#1 Sample Questions |
Exam1
(example).pdf |
| |
Exam
#1 Sample Questions (with solutions) |
Exam1
(example with solutions).pdf |
| Lecture 15 |
Optimized
Implementation of Logic Functions: Multilevel Synthesis and Analysis |
LECT15.pdf |
| Lecture 16 |
Number
Representation and Arithmetic Circuits: Number Representation and Unsigned
Addition |
LECT16.pdf |
| Lecture 17 |
Number
Representation and Arithmetic Circuits: Signed Numbers, Binary Adders and
Subtractors |
LECT17.pdf |
| Lecture 18 |
Number
Representation and Arithmetic Circuits: Fast Adder Designs, Tradeoffs, and
Examples |
LECT18.pdf |
| Lecture 19 |
Number
Representation and Arithmetic Circuits: Design of Arithmetic Circuits Using
CAD Tools |
LECT19.pdf |
| Lecture 20 |
Number
Representation and Arithmetic Circuits: Other Number Representations |
LECT20.pdf |
| Lecture 21 |
Combinatorial
Circuit Building Blocks: Multiplexers |
LECT21.pdf |
| Lecture 22 |
Combinatorial
Circuit Building Blocks: Decoders, Demultiplexers, Encoders and Code
Converters |
LECT22.pdf |
| Lecture 23 |
Combinatorial
Circuit Building Blocks: VHDL for Combinational Circuits |
LECT23.pdf |
| Lecture 24 |
Flip-Flops,
Registers and Counters: Latches |
LECT24.pdf |
| Lecture 25 |
Flip-Flops,
Registers and Counters: Flip-Flops |
LECT25.pdf |
| Lecture 26 |
Flip-Flops,
Registers and Counters: Registers and Counters |
LECT26.pdf |
| Lecture 27 |
Synchronous
Sequential Circuits: State Diagrams, State Tables |
LECT27.pdf |
| |
Exam
#2 Sample Questions |
Exam2
(example).pdf |
| |
Exam
#2 Sample Questions (with solutions) |
Exam2
(example with solutions).pdf |
| Lecture 28 |
Synchronous
Sequential Circuits: Implementations using D-type, T-type and JK-type
Flip-Flops |
LECT28.pdf |
| Lecture 29 |
Synchronous
Sequential Circuits: State Assignment Problem, Mealy State Machines |
LECT29.pdf |
| Lecture 30 |
VHDL
for Sequential Circuits |
LECT30.pdf |
| Lecture 31 |
Design
of Finite State Machines Using CAD Tools |
LECT31.pdf |
| Lecture 32 |
State
Minimization |
LECT32.pdf |